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R&D Engineering, Sr Staff Engineer - 10360

click.appcast.io - Synopsys - Boxborough, MA

1 day ago - Are: At Synopsys, we drive the hiring process. At Synopsys, we want talented people of - Save Job - Email - More

View Job Details : R&D Engineering, Sr Staff Engineer - 10360
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ASIC Engineering Technical Leader - SDC

click.appcast.io - Cisco Systems, Inc. - California, MO

1 day ago - . * Experience with synthesis tools (e.g., Synopsys DC/DCG/FC) and Verilog/SystemVerilog - Save Job - Email - More

View Job Details : ASIC Engineering Technical Leader - SDC
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ASIC Engineering Technical Leader - SDC

click.appcast.io - Cisco Systems, Inc. - San Jose, CA

1 day ago - . * Experience with synthesis tools (e.g., Synopsys DC/DCG/FC) and Verilog/SystemVerilog - Save Job - Email - More

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Senior RTL Design Engineer

click.appcast.io - Seneca Resources - Santa Clara, CA

6 days ago - Gate-Level Simulations (GLS) using Synopsys VCS and Verdi * Develop and deliver SoC-level - Save Job - Email - More

View Job Details : Senior RTL Design Engineer
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SDC Engineer (eInfochips Inc)

click.appcast.io - Arrow Electronics, Inc. - San Jose, CA

3 days ago - async boundaries) * Experience with synthesis tools (eg. Synopsys DC/DCG/FC), Verilog/System - Save Job - Email - More

View Job Details : SDC Engineer (eInfochips Inc)
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Static Timing Analysis Engineer

click.appcast.io - Pro Integrate - San Jose, CA

3 days ago - async boundaries) * Experience with synthesis tools (eg. Synopsys DC/DCG/FC), Verilog/System - Save Job - Email - More

View Job Details : Static Timing Analysis Engineer
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ASIC Engineering Technical Leader - SDC

click.appcast.io - Cisco Systems, Inc. - San Jose, CA

2 days ago - boundaries). * Experience with synthesis tools (eg. Synopsys DC/DCG/FC), Verilog/System - Save Job - Email - More

View Job Details : ASIC Engineering Technical Leader - SDC
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ASIC DESIGN FOR TEST ENGINEER - Acacia

click.appcast.io - Cisco - San Jose, CA

1 day ago - techniques, ATPG, and post-silicon DVT. * Proficiency with Synopsys/Mentor DFT tools. Preferred Qualifications - Save Job - Email - More

View Job Details : ASIC DESIGN FOR TEST ENGINEER - Acacia
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DevOps for Emulation

www.ziprecruiter.com - Etched - San Jose, CA

30+ days ago - pipelines, specifically focusing on integrating GitHub, Synopsys Zebu emulation platforms, and related EDA tool flows - Save Job - Email - More

View Job Details : DevOps for Emulation
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ASIC Design Engineer - Design & Timing Constraints

click.appcast.io - Cisco Systems, Inc. - San Jose, CA

2 days ago - async boundaries) * Experience with synthesis tools (eg. Synopsys DC/DCG/FC), Verilog/System - Save Job - Email - More

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ASIC Design Engineer - Design & Timing Constraints

click.appcast.io - Cisco Systems, Inc. - San Jose, CA

1 day ago - . * Experience with synthesis tools (e.g., Synopsys DC, FC), and Verilog/SystemVerilog programming - Save Job - Email - More

View Job Details : ASIC Design Engineer - Design & Timing Constraints
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ASIC Design Engineer - Design & Timing Constraints

click.appcast.io - Cisco Systems, Inc. - California, MO

1 day ago - . * Experience with synthesis tools (e.g., Synopsys DC, FC), and Verilog/SystemVerilog programming - Save Job - Email - More

View Job Details : ASIC Design Engineer - Design & Timing Constraints
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ASIC Design Technical Leader - Design & Timing Constraints Focus

click.appcast.io - Cisco Systems, Inc. - San Jose, CA

2 days ago - async boundaries) * Experience with synthesis tools (eg. Synopsys DC/DCG/FC), Verilog/System - Save Job - Email - More

View Job Details : ASIC Design Technical Leader - Design & Timing Constraints Focus
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Pre - Silicon Verification Technical Lead Engineer

click.appcast.io - Advanced Micro Devices, Inc. - California, MO

1 day ago - benches and usage of simulation tools/debug environments such as Synopsys VCS or Cadence Xcelium. * Require strong - Save Job - Email - More

View Job Details : Pre - Silicon Verification Technical Lead Engineer
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Pre - Silicon Verification Technical Lead Engineer

click.appcast.io - Advanced Micro Devices, Inc. - San Jose, CA

1 day ago - benches and usage of simulation tools/debug environments such as Synopsys VCS or Cadence Xcelium. * Require strong - Save Job - Email - More

View Job Details : Pre - Silicon Verification Technical Lead Engineer
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Senior Electronic Design Engineer / Manager

click.appcast.io - JRC Integrated Systems - Sunnyvale, CA

1 day ago - experience in electronic chip and semiconductor design using Cadence or Synopsys design flows. * Experience with synthesis, place and route ( - Save Job - Email - More

View Job Details : Senior Electronic Design Engineer / Manager
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Principal Analog and Mixed-Signal Circuit Designer

click.appcast.io - Synopsys, Inc. - Sunnyvale, CA

1 day ago - Are: At Synopsys, we drive the innovationsExperience with schematic entry in Synopsys Custom Designer - Save Job - Email - More

View Job Details : Principal Analog and Mixed-Signal Circuit Designer
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ASIC Verification Engineer (UVM/SOC)

click.appcast.io - TPI Global Solutions - Santa Clara, CA

4 days ago - /O, or similar). * Hands-on experience with Cadence/Synopsys verification tools . * Bachelor’s or Master - Save Job - Email - More

View Job Details : ASIC Verification Engineer (UVM/SOC)
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SoC Design Verification Engineer

click.appcast.io - Encore Semi Llc - San Diego, CA

1 day ago - Level Simulations • Experience with Synopsys tools VCS & Verdi • Python Scripting - Save Job - Email - More

View Job Details : SoC Design Verification Engineer
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SoC Design Verification Engineer San Diego, CA

click.appcast.io - Encore Semi Llc - San Diego, CA

1 day ago - Level Simulations • Experience with Synopsys tools VCS & Verdi • Python Scripting - Save Job - Email - More

View Job Details : SoC Design Verification Engineer San Diego, CA
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