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  1. Physical Design Engineer - Mixed Signal IP

    de.jobsyn.org - Qualcomm - San Diego, CA
    14 days ago - Experience with industry leading tools + Cadence + Synopsys + Mentor + Ansys + Working knowledge of programming - Save Job - - More

    View Job Details : Physical Design Engineer - Mixed Signal IP

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  2. SoC Physical Design Verification Engineer

    de.jobsyn.org - Apple - San Diego, CA
    12 days ago - used for physical verification: Mentor Calibre, and/or Synopsys ICV. + Tapeout experience with a track record of successful signoff - Save Job - - More

    View Job Details : SoC Physical Design Verification Engineer

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  3. Senior Lead Engineer, Hardware Design

    de.jobsyn.org - Celestica - Penang, Mys
    20 days ago - preferred), Sigrity Power SI. • Experience with Synopsys HSPICE and/or Keysight ADS for both time and frequency - Save Job - - More

    View Job Details : Senior Lead Engineer, Hardware Design

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  4. Senior Lead Engineer, Hardware Design

    de.jobsyn.org - Celestica - Penang, Mys
    20 days ago - preferred), Sigrity Power SI. • Experience with Synopsys HSPICE and/or Keysight ADS for both time and frequency - Save Job - - More

    View Job Details : Senior Lead Engineer, Hardware Design

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  5. Physical Design Lead – Custom Silicon Management

    de.jobsyn.org - Apple - Austin, TX
    20 days ago - of at least one of the industry CAD tools - Cadence, Synopsys, Mentor or Atoptech. + Proficient in Static - Save Job - - More

    View Job Details : Physical Design Lead – Custom Silicon Management

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  6. Staff SOC Mixed Signal Engineer

    de.jobsyn.org - Qualcomm - San Diego, CA
    9 hours ago - ’s using state-of-the-art tools (from Cadence, Synopsys, etc.) and deep sub-micron technology nodes(4nm, 3nm). Work with - Save Job - - More

    View Job Details : Staff SOC Mixed Signal Engineer

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  7. Network Packet Processing Core DV Sr Engineer

    de.jobsyn.org - Qualcomm - Bangalore, Ind
    20 days ago - C. + HW verification using Cadence and Synopsys simulator tools, SV/UVM based TB development - Save Job - - More

    View Job Details : Network Packet Processing Core DV Sr Engineer

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  8. Network Packet Processing Core DV Sr Engineer

    de.jobsyn.org - Qualcomm - Bangalore, Ind
    20 days ago - C. + HW verification using Cadence and Synopsys simulator tools, SV/UVM based TB development - Save Job - - More

    View Job Details : Network Packet Processing Core DV Sr Engineer

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  9. Senior Analog Layout Engineer

    de.jobsyn.org - Capgemini - Santa Clara, CA
    20 days ago - thermal and electro migration-aware techniques. + Proficient in Synopsys, Cadence, and Mentor layout tools; Python scripting - Save Job - - More

    View Job Details : Senior Analog Layout Engineer

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  10. Physical Synthesis Implementation Engineer

    de.jobsyn.org - Qualcomm - San Diego, CA
    18 days ago - required upon entry)** + Familiarity with EDA tools such as Synopsys Design Compiler, Cadence Genus, or similar - Save Job - - More

    View Job Details : Physical Synthesis Implementation Engineer

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  11. Sr Staff GPU Physical Design Engineer

    de.jobsyn.org - Qualcomm - Noida, Ind
    20 days ago - Well versed with the Block level PnR convergence with Synopsys ICC2/ Cadence Innovus and timing convergence - Save Job - - More

    View Job Details : Sr Staff GPU Physical Design Engineer

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  12. Staff GPU Physical Design Engineer

    de.jobsyn.org - Qualcomm - Bangalore, Ind
    20 days ago - Well versed with the Block level PnR convergence with Synopsys ICC2/ Cadence Innovus and timing convergence - Save Job - - More

    View Job Details : Staff GPU Physical Design Engineer

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  13. GPU Physical Design Engineer (Sr Lead/Staff)

    de.jobsyn.org - Qualcomm - Bangalore, Ind
    11 days ago - Well versed with the Block level PnR convergence with Synopsys ICC2/ Cadence Innovus and timing convergence - Save Job - - More

    View Job Details : GPU Physical Design Engineer (Sr Lead/Staff)

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  14. Design Engineering Manager 2

    de.jobsyn.org - Northrop Grumman - Annapolis Junction, MD
    4 days ago - Proficient in the use of commercial CAD software (Cadence, Synopsys, Mentor Graphics) in the design, layout, or verification - Save Job - - More

    View Job Details : Design Engineering Manager 2

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  15. Design Engineering Manager 2

    de.jobsyn.org - Northrop Grumman - Linthicum Heights, MD
    4 days ago - Proficient in the use of commercial CAD software (Cadence, Synopsys, Mentor Graphics) in the design, layout, or verification - Save Job - - More

    View Job Details : Design Engineering Manager 2

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  16. Senior Analog Layout Engineer

    de.jobsyn.org - Capgemini - San Francisco, CA
    20 days ago - industry standard EDA tools from Cadence, Mentor and Synopsys for silicon chip design and production. + ·Must be able to set up LVS, DRC - Save Job - - More

    View Job Details : Senior Analog Layout Engineer

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  17. Senior Analog Layout Engineer

    de.jobsyn.org - Capgemini - San Jose, CA
    20 days ago - industry standard EDA tools from Cadence, Mentor and Synopsys for silicon chip design and production. + ·Must be able to set up LVS, DRC - Save Job - - More

    View Job Details : Senior Analog Layout Engineer

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  18. COOK (FULL TIME)

    de.jobsyn.org - Compass Group, North America - Sunnyvale, CA
    4 days ago - immediately for full time COOK positions. + Location: Synopsys - 800 North Mary Avenue, Sunnyvale, CA 94085 - Save Job - - More

    View Job Details : COOK (FULL TIME)

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  19. FPGA Verification Engineer, Kuiper Payload FPGA

    de.jobsyn.org - Amazon - Redmond, WA
    20 days ago - with FPGA/ASIC design and verification tools (Synopsys, Vivado, Quartus) • Experience monitoring - Save Job - - More

    View Job Details : FPGA Verification Engineer, Kuiper Payload FPGA

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  20. FPGA Verification Engineer, Kuiper Payload FPGA

    de.jobsyn.org - Amazon - Sunnyvale, CA
    20 days ago - with FPGA/ASIC design and verification tools (Synopsys, Vivado, Quartus) • Experience monitoring - Save Job - - More

    View Job Details : FPGA Verification Engineer, Kuiper Payload FPGA

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