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Physical Synthesis Implementation Engineer

de.jobsyn.org - Qualcomm - San Diego, CA

16 days ago - required upon entry)** + Familiarity with EDA tools such as Synopsys Design Compiler, Cadence Genus, or similar - Save Job - Email - More

View Job Details : Physical Synthesis Implementation Engineer
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GPU Physical Design Engineer (Sr Lead/Staff)

de.jobsyn.org - Qualcomm - Bangalore, Ind

9 days ago - Well versed with the Block level PnR convergence with Synopsys ICC2/ Cadence Innovus and timing convergence - Save Job - Email - More

View Job Details : GPU Physical Design Engineer (Sr Lead/Staff)
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Staff GPU Physical Design Engineer

de.jobsyn.org - Qualcomm - Bangalore, Ind

18 days ago - Well versed with the Block level PnR convergence with Synopsys ICC2/ Cadence Innovus and timing convergence - Save Job - Email - More

View Job Details : Staff GPU Physical Design Engineer
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Sr Staff GPU Physical Design Engineer

de.jobsyn.org - Qualcomm - Noida, Ind

18 days ago - Well versed with the Block level PnR convergence with Synopsys ICC2/ Cadence Innovus and timing convergence - Save Job - Email - More

View Job Details : Sr Staff GPU Physical Design Engineer
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Design Engineering Manager 2

de.jobsyn.org - Northrop Grumman - Linthicum Heights, MD

2 days ago - Proficient in the use of commercial CAD software (Cadence, Synopsys, Mentor Graphics) in the design, layout, or verification - Save Job - Email - More

View Job Details : Design Engineering Manager 2
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Design Engineering Manager 2

de.jobsyn.org - Northrop Grumman - Annapolis Junction, MD

2 days ago - Proficient in the use of commercial CAD software (Cadence, Synopsys, Mentor Graphics) in the design, layout, or verification - Save Job - Email - More

View Job Details : Design Engineering Manager 2
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Senior Analog Layout Engineer

de.jobsyn.org - Capgemini - San Jose, CA

19 days ago - industry standard EDA tools from Cadence, Mentor and Synopsys for silicon chip design and production. + ·Must be able to set up LVS, DRC - Save Job - Email - More

View Job Details : Senior Analog Layout Engineer
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Senior Analog Layout Engineer

de.jobsyn.org - Capgemini - San Francisco, CA

19 days ago - industry standard EDA tools from Cadence, Mentor and Synopsys for silicon chip design and production. + ·Must be able to set up LVS, DRC - Save Job - Email - More

View Job Details : Senior Analog Layout Engineer
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COOK (FULL TIME)

de.jobsyn.org - Compass Group, North America - Sunnyvale, CA

3 days ago - immediately for full time COOK positions. + Location: Synopsys - 800 North Mary Avenue, Sunnyvale, CA 94085 - Save Job - Email - More

View Job Details : COOK (FULL TIME)
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FPGA Verification Engineer, Kuiper Payload FPGA

de.jobsyn.org - Amazon - Sunnyvale, CA

19 days ago - with FPGA/ASIC design and verification tools (Synopsys, Vivado, Quartus) • Experience monitoring - Save Job - Email - More

View Job Details : FPGA Verification Engineer, Kuiper Payload FPGA
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FPGA Verification Engineer, Kuiper Payload FPGA

de.jobsyn.org - Amazon - Redmond, WA

19 days ago - with FPGA/ASIC design and verification tools (Synopsys, Vivado, Quartus) • Experience monitoring - Save Job - Email - More

View Job Details : FPGA Verification Engineer, Kuiper Payload FPGA
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Senior Synthesis &STA Engineer

de.jobsyn.org - Capgemini - Colorado, CO

4 days ago - Proficiency with industry-standard ASIC EDA tools, especially Synopsys Design Compiler and PrimeTime. + Strong - Save Job - Email - More

View Job Details : Senior Synthesis &STA Engineer
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Senior Electrical Engineer (FPGA Design) 1

de.jobsyn.org - L3Harris - Camden, NJ

19 days ago - Crossing (RDC), Questa Lint, Synopsys (DC/Primetime/Synplify), Xilinx/Intel - Save Job - Email - More

View Job Details : Senior Electrical Engineer (FPGA Design) 1
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Semiconductor Technical Program Manager

de.jobsyn.org - Capgemini - San Francisco, CA

3 days ago - required** **ASIC Design flow/Methodology** **Synopsys/Cadence EDA Tools** **Python** **Mandatory - Save Job - Email - More

View Job Details : Semiconductor Technical Program Manager
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Design Methodology Engineer

de.jobsyn.org - Qualcomm - San Diego, CA

18 days ago - power. The engineer should be proficient in static timing analysis using the Synopsys Primetime toolset and should have strong coding skills in scripting - Save Job - Email - More

View Job Details : Design Methodology Engineer
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Systems Architect – Display Sub-System

de.jobsyn.org - Qualcomm - Bangalore, Ind

18 days ago - Verilog/VHDL and digital hardware design tools such as Synopsys/Cadence/Mentor ASIC design and simulation tool - Save Job - Email - More

View Job Details : Systems Architect – Display Sub-System
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Systems Architect – Display Sub-System

de.jobsyn.org - Qualcomm - Bangalore, Ind

18 days ago - Verilog/VHDL and digital hardware design tools such as Synopsys/Cadence/Mentor ASIC design and simulation tool - Save Job - Email - More

View Job Details : Systems Architect – Display Sub-System
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STA Engineer

de.jobsyn.org - Apple - Cupertino, CA

19 days ago - Constraint analysis and debug, using industry standard tools such as Synopsys GCA (Galaxy Constraint Analyzer) is desirable - Save Job - Email - More

View Job Details : STA Engineer
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STA Engineer

de.jobsyn.org - Apple - Cupertino, CA

19 days ago - Constraint analysis and debug, using industry standard tools such as Synopsys GCA (Galaxy Constraint Analyzer) is desirable - Save Job - Email - More

View Job Details : STA Engineer
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Integration Engineer

de.jobsyn.org - Apple - Santa Clara, CA

5 days ago - Familiarity with SoC design flows and tools (e.g., Synopsys, Cadence). + Experience with bus protocols ( - Save Job - Email - More

View Job Details : Integration Engineer
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