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Senior ASIC Timing Engineer

de.jobsyn.org - NVIDIA - Westford, MA

18 days ago - Power user of Static Timing tools like Synopsys PrimeTime or Cadence Tempus. + Solid experience - Save Job - Email - More

View Job Details : Senior ASIC Timing Engineer
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Physical Design - Sr engineer

de.jobsyn.org - Qualcomm - Chennai, Ind

18 days ago - concepts + Knowledge in Block level PnR convergence with Synopsys ICC2/ Cadence Innovus and timing convergence in PTSI - Save Job - Email - More

View Job Details : Physical Design - Sr engineer
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Physical Design - engineer

de.jobsyn.org - Qualcomm - Chennai, Ind

2 days ago - concepts + Knowledge in Block level PnR convergence with Synopsys ICC2/ Cadence Innovus and timing convergence in PTSI - Save Job - Email - More

View Job Details : Physical Design - engineer
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Mixed-Signal Design Verification and Validation Engineer

de.jobsyn.org - Broadcom - San Jose, CA

18 days ago - verification + Hands-on knowledge of standard industry EDA tools - Synopsys/Cadence + Experienced with GLS with & without parasitic - Save Job - Email - More

View Job Details : Mixed-Signal Design Verification and Validation Engineer
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ASIC Engineering Technical Leader

de.jobsyn.org - Cisco - Bangalore, Ind

18 days ago - used for physical verification such as Mentor Calibre, Synopsys ICV, etc. * Experience in planning physical verification - Save Job - Email - More

View Job Details : ASIC Engineering Technical Leader
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Physical Design - Sr engineer

de.jobsyn.org - Qualcomm - Chennai, Ind

2 days ago - versed with the Block level PnR convergence with Synopsys ICC2/ Cadence Innovus and timing convergence in PTSI - Save Job - Email - More

View Job Details : Physical Design - Sr engineer
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Senior Pixel Designer

de.jobsyn.org - Teledyne - Waterloo, ON

18 days ago - simulations (process/device/optoelectronic simulations using Synopsys, Silvaco) and optical simulations (Ray tracing/ - Save Job - Email - More

View Job Details : Senior Pixel Designer
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ASIC DESIGN FOR TEST ENGINEER - Acacia

de.jobsyn.org - Cisco - San Jose, CA

18 days ago - techniques, ATPG and post-silicon DVT * Prior experience with Synopsys/Mentor DFT tools Preferred Qualifications - Save Job - Email - More

View Job Details : ASIC DESIGN FOR TEST ENGINEER - Acacia
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ASIC DESIGN FOR TEST ENGINEER - Acacia

de.jobsyn.org - Cisco - Maynard, MA

18 days ago - techniques, ATPG and post-silicon DVT * Prior experience with Synopsys/Mentor DFT tools Preferred Qualifications - Save Job - Email - More

View Job Details : ASIC DESIGN FOR TEST ENGINEER - Acacia
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Senior Application Engineer (AE) - Aprisa P&R

de.jobsyn.org - Siemens - Hsinchu, Twn

18 days ago - IC design space + Expertise with Cadence Innovus, Synopsys IC Compiler I/II, Avatar Aprisa - Save Job - Email - More

View Job Details : Senior Application Engineer (AE) - Aprisa P&R
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STA Engineer

de.jobsyn.org - Broadcom - San Jose, CA

18 days ago - constraints for intricate SoC designs. + Experience with Synopsys TCM tool. + Perform static timing analysis (STA) - Save Job - Email - More

View Job Details : STA Engineer
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VLSI Technical Design and Verification Engineer

de.jobsyn.org - Broadcom - Bangalore Electronic City S2, Ind

18 days ago - tools and Verification environments (e.g., Cadence, Synopsys, UVM). + Expertise in various communication protocols - Save Job - Email - More

View Job Details : VLSI Technical Design and Verification Engineer
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Global Alliance Manager, Developer Relations - Cadence

de.jobsyn.org - NVIDIA - Santa Clara, CA

18 days ago - Experience working at or with EDA companies (e.g. Cadence, Synopsys, Siemens EDA) with validated understanding of EDA - Save Job - Email - More

View Job Details : Global Alliance Manager, Developer Relations - Cadence
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Senior Async and IO Timing Methodology Engineer

de.jobsyn.org - NVIDIA - Santa Clara, CA

18 days ago - flow development. + Experience working with STA tools like Synopsys PrimeTime or Cadence Tempus. + Deep understanding - Save Job - Email - More

View Job Details : Senior Async and IO Timing Methodology Engineer
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Senior ASIC Design Engineer - GPU

de.jobsyn.org - NVIDIA - Madison, AL

8 days ago - VCS or equivalent simulation tools, debug tools like Verdi, Synopsys) + A solid understanding of Object Oriented - Save Job - Email - More

View Job Details : Senior ASIC Design Engineer - GPU
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Analog Mixed Signal Layout Designer

de.jobsyn.org - Broadcom - San Jose, CA

18 days ago - standard EDA tools from Cadence, Mentor and Synopsys. + Experience with layout of high-performance high-speed analog mixed-signal - Save Job - Email - More

View Job Details : Analog Mixed Signal Layout Designer
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Senior Engineer - PNR/STA

de.jobsyn.org - Broadcom - Yishun, Sgp

18 days ago - .vs. ICC timing reports. + Complete exposure to Synopsys Timing closure tools; Star-RC, Prime - Save Job - Email - More

View Job Details : Senior Engineer - PNR/STA
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Senior Engineer- PNR/STA

de.jobsyn.org - Broadcom - Yishun, Sgp

18 days ago - .vs. ICC timing reports. + Complete exposure to Synopsys Timing closure tools; Star-RC, Prime - Save Job - Email - More

View Job Details : Senior Engineer- PNR/STA
Research Tools: More information about jobs in Yishun, Sgp
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Physical design Engineer

de.jobsyn.org - Qualcomm - Chennai, Ind

18 days ago - versed with the Block level PnR convergence with Synopsys ICC2/ Cadence Innovus and timing convergence in PTSI - Save Job - Email - More

View Job Details : Physical design Engineer
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Low Power ASIC Engineer - New College Grad 2025

de.jobsyn.org - NVIDIA - Santa Clara, CA

11 days ago - Must be experienced with Incisive Low-Power or Synopsys VCS NLP + Strong debug skills and experience with - Save Job - Email - More

View Job Details : Low Power ASIC Engineer - New College Grad 2025
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