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Mixed-Signal IC Design Engineer

de.jobsyn.org - Apple - San Diego, CA

8 hours ago - ADC/DAC architectures, performance metrics, design trade-offs, and criteria for deciding which ADC/DAC designs - Save Job - Email - More

View Job Details : Mixed-Signal IC Design Engineer
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Mixed-Signal IC Design Engineer

de.jobsyn.org - Apple - San Diego, CA

8 hours ago - ADC/DAC architectures, performance metrics, design trade-offs, and criteria for deciding which ADC/DAC designs - Save Job - Email - More

View Job Details : Mixed-Signal IC Design Engineer
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Mixed-Signal IC Design Engineer

de.jobsyn.org - Apple - Beaverton, OR

8 hours ago - ADC/DAC architectures, performance metrics, design trade-offs, and criteria for deciding which ADC/DAC designs - Save Job - Email - More

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DFT Design Engineer, AWS Machine Learning Acceleration

click.appcast.io - Amazon - Seattle, WA

1 day ago - ATPG, JTAG, MBIST and trade-offs between test quality and testknowledge of design verification (DV) simulation methodologies - Experience - Save Job - Email - More

View Job Details : DFT Design Engineer, AWS Machine Learning Acceleration
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GPU SoC Lead

de.jobsyn.org - Intel - Folsom, CA

3 days ago - requirements + Making appropriate design trade off balancing risk, area, powerArea efficient RTL logic design, and DV support + Running tools - Save Job - Email - More

View Job Details : GPU SoC Lead
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GPU SoC Lead

de.jobsyn.org - Intel - Hillsboro, OR

3 days ago - requirements + Making appropriate design trade off balancing risk, area, powerArea efficient RTL logic design, and DV support + Running tools - Save Job - Email - More

View Job Details : GPU SoC Lead
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GPU Logic Design Engineer

de.jobsyn.org - Intel - Santa Clara, CA

3 days ago - requirements + Making appropriate design trade off balancing risk, area, powerArea efficient RTL logic design and DV support + Running tools - Save Job - Email - More

View Job Details : GPU Logic Design Engineer
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GPU SoC Lead

de.jobsyn.org - Intel - Santa Clara, CA

3 days ago - requirements + Making appropriate design trade off balancing risk, area, powerArea efficient RTL logic design, and DV support + Running tools - Save Job - Email - More

View Job Details : GPU SoC Lead
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GPU Logic Design Engineer

de.jobsyn.org - Intel - Phoenix, AZ

3 days ago - requirements + Making appropriate design trade off balancing risk, area, powerArea efficient RTL logic design and DV support + Running tools - Save Job - Email - More

View Job Details : GPU Logic Design Engineer
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GPU SoC Lead

de.jobsyn.org - Intel - Phoenix, AZ

3 days ago - requirements + Making appropriate design trade off balancing risk, area, powerArea efficient RTL logic design, and DV support + Running tools - Save Job - Email - More

View Job Details : GPU SoC Lead
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GPU Logic Design Engineer

de.jobsyn.org - Intel - Folsom, CA

3 days ago - requirements + Making appropriate design trade off balancing risk, area, powerArea efficient RTL logic design and DV support + Running tools - Save Job - Email - More

View Job Details : GPU Logic Design Engineer
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GPU Logic Design Engineer

de.jobsyn.org - Intel - Hillsboro, OR

3 days ago - requirements + Making appropriate design trade off balancing risk, area, powerArea efficient RTL logic design and DV support + Running tools - Save Job - Email - More

View Job Details : GPU Logic Design Engineer
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Security Vetting Administrator

de.jobsyn.org - AECOM - Basingstoke, Gbr

3 days ago - ll get all the benefits of being a part of a global, publicly traded firm – access to industry-leading technology and thinking and transformational - Save Job - Email - More

View Job Details : Security Vetting Administrator
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Night Trader - DV Equities

www.ziprecruiter.com - DV Trading - New York, NY

4 days ago - Europe. Since spinning out of a large brokerage firm in 2016, DV Trading has rapidly scaled as an independent proprietary trading firm - Save Job - Email - More

View Job Details : Night Trader - DV Equities
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National Air Logistics Sales Manager

de.jobsyn.org - Kuehne+Nagel - Gurugram, Ind

4 days ago - freight/logistics + Deep understanding of air freight products, international trade, and regulatory frameworks + Strong negotiation, communication, and presentation - Save Job - Email - More

View Job Details : National Air Logistics Sales Manager
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Mixed-Signal IC Design Engineer

de.jobsyn.org - Apple - Cupertino, CA

4 days ago - ADC/DAC architectures, performance metrics, design trade-offs, and criteria for deciding which ADC/DAC designs - Save Job - Email - More

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Mixed-Signal IC Design Engineer

de.jobsyn.org - Apple - Cupertino, CA

4 days ago - ADC/DAC architectures, performance metrics, design trade-offs, and criteria for deciding which ADC/DAC designs - Save Job - Email - More

View Job Details : Mixed-Signal IC Design Engineer
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Mixed-Signal IC Design Engineer

de.jobsyn.org - Apple - Beaverton, OR

4 days ago - ADC/DAC architectures, performance metrics, design trade-offs, and criteria for deciding which ADC/DAC designs - Save Job - Email - More

View Job Details : Mixed-Signal IC Design Engineer
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GRO Technician Trainee

www.ziprecruiter.com - Holt Ag Solutions, LLC - Willows, CA

6 days ago - Equal Opportunity Employer M/F/V/DV. Holt provides equal employment opportunities (EEO - Save Job - Email - More

View Job Details : GRO Technician Trainee
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GRO Technician Trainee

www.ziprecruiter.com - Holt Ag Solutions, LLC - Willows, CA

6 days ago - Equal Opportunity Employer M/F/V/DV. Holt provides equal employment opportunities (EEO - Save Job - Email - More

View Job Details : GRO Technician Trainee
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