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  1. de.jobsyn.org - Siemens Digital Industries Software - Bangalore, Ind
    1 hour ago - Hands-on experience using commercial synthesis tools like Synopsys-DC/FC, Cadence-Genus is a must. + - Save Job - - More

    View Job Details : Lead Product Engineer (Synthesis)

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  2. de.jobsyn.org - Qualcomm - Sophia Antipolis, Fra
    1 hour ago - SystemVerilog, SystemC, Cadence NCSIM, Synopsys VCS / Verdi, Git, Svn database management - Save Job - - More
  3. www.jobg8.com - University of Colorado Boulder - Boulder, CO
    13 hours ago - , and modeling tools (Cadence, Synopsys, SPICE, COMSOL, etc.) Experience with data/numerical - Save Job - - More

    View Job Details : Research Associate

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  4. de.jobsyn.org - Qualcomm - San Diego, CA
    22 hours ago - Experience with Verilog/SystemVerilog design, Synopsys synthesis, low power design, test plan development, coverage-based design verification - Save Job - - More

    View Job Details : Graphics ASICS Hardware Design Engineer (San Diego/Santa Clara/Austin/Boxborough)

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  5. de.jobsyn.org - Qualcomm - Bangalore, Ind
    22 hours ago - Design (Verilog RTL design, System Verilog, Synopsys Design Compiler, Cadence RTL Compiler - Save Job - - More

    View Job Details : PHYSICAL DESIGN ENGINEER

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  6. de.jobsyn.org - Qualcomm - Santa Clara, CA
    22 hours ago - Implementation/Synthesis + Strong Expertise with Synopsys/Cadence ASIC Synthesis tools and - Save Job - - More

    View Job Details : Synthesis/STA Engineer

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  7. de.jobsyn.org - Intel - 
    23 hours ago - analysis or post-silicon validation field(s). + Good foundation in Synopsys tools such as PrimeTime-PX and PrimePower - Save Job - - More

    View Job Details : Chipsets Power Simulation and Analysis Engineer

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  8. de.jobsyn.org - Intel - Hillsboro, OR
    23 hours ago - Experience in: + Experience with integrated circuit design tools (ex: Synopsys/Cadence), including logic synthesis, place and route, static timing analysis - Save Job - - More

    View Job Details : Physical Design Engineer For CPU Core IP

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  9. de.jobsyn.org - Intel - Santa Clara, CA
    23 hours ago - tools. + 3+ years of experience with pre-silicon simulation tool flows such as Synopsys VCS Verdi and DVE. + 3+ years of experience in OVM - Save Job - - More

    View Job Details : Design Verification Engineer

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  10. de.jobsyn.org - Intel - Santa Clara, CA
    23 hours ago - tools. + 3+ years of experience with pre-silicon simulation tool flows such as Synopsys VCS Verdi and DVE. + 3+ years of experience in OVM - Save Job - - More

    View Job Details : Design Verification Engineer

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  11. de.jobsyn.org - Global Foundries - Karnataka, Ind
    23 hours ago - experience with EDA (Cadence, Mentor Graphics, Synopsys…) tools for schematic design & simulations (Virtuoso - Save Job - - More

    View Job Details : Memory IP Design - (MTPM/OTP/MRAM/SRAM/eFlash)

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  12. click.appcast.io - Ixana - West Lafayette, IN
    1 day ago - CMOS technologies • Working knowledge of Cadence/Synopsys design, simulation, layout, and verification tools • Knowledge - Save Job - - More

    View Job Details : NSF Postdoctoral Fellow - IC Design

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  13. www.talent.com - JBA International - Null, CA
    1 day ago - Proficiency in EDA tools such as Cadence Virtuoso, Synopsys Design Compiler, and Mentor Graphics - Save Job - - More

    View Job Details : Semiconductor Engineer

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  14. www.talent.com - ACL Digital - Westford, MA
    1 day ago - CD) for our product application teams and preferably possess knowledge of Synopsys Black Duck Software Composition Analysis - Save Job - - More

    View Job Details : Senior Application Security Engineer

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  15. www.talent.com - L&T Technology Services - Sunnyvale, CA
    1 day ago - preferred. Expertise in Cadence (Innovus) P&R, Synopsys PrimeTime/StarRC/ICV, Ansys Redhawk, and - Save Job - - More

    View Job Details : Physical Design Engineer

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  16. de.jobsyn.org - Intel - Carson City, NV
    1 day ago - designs.Physical synthesis, place and route, and clock tree synthesis with Synopsys or Cadence tools.Static timing analysis constraint understanding - Save Job - - More

    View Job Details : SOC Design Engineer - Physical design and Integration

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  17. de.jobsyn.org - Intel - Topeka, KS
    1 day ago - designs.Physical synthesis, place and route, and clock tree synthesis with Synopsys or Cadence tools.Static timing analysis constraint understanding - Save Job - - More

    View Job Details : SOC Design Engineer - Physical design and Integration

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  18. de.jobsyn.org - Intel - Little Rock, AR
    1 day ago - designs.Physical synthesis, place and route, and clock tree synthesis with Synopsys or Cadence tools.Static timing analysis constraint understanding - Save Job - - More

    View Job Details : SOC Design Engineer - Physical design and Integration

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  19. de.jobsyn.org - Intel - Charleston, WV
    1 day ago - designs.Physical synthesis, place and route, and clock tree synthesis with Synopsys or Cadence tools.Static timing analysis constraint understanding - Save Job - - More

    View Job Details : SOC Design Engineer - Physical design and Integration

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  20. de.jobsyn.org - Intel - Montgomery, AL
    1 day ago - designs.Physical synthesis, place and route, and clock tree synthesis with Synopsys or Cadence tools.Static timing analysis constraint understanding - Save Job - - More

    View Job Details : SOC Design Engineer - Physical design and Integration

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