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Senior Applications Engineer (Aprisa Place & Route)

de.jobsyn.org - Siemens Digital Industries Software - Tokyo, Jpn

30+ days ago - EDAまたはIC設計領域における5年以上の業界経験・Cadence Innovus、Synopsys IC Compiler I/II、Atoptech/ - Save Job - Email - More

View Job Details : Senior Applications Engineer (Aprisa Place & Route)
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DFT Sr. Staff Engineer

click.appcast.io - Collabera - Phoenix, AZ

12 hours ago - such as TCL/Perl/Python * Experience with Synopsys DFT tools and IEEE standards 1149.1 and 1149 - Save Job - Email - More

View Job Details : DFT Sr. Staff Engineer
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Hardware Design Engineer (ASIC)

de.jobsyn.org - Edgecortix Inc. - Remote, Jpn

30+ days ago - Experience in performing logic synthesis using Cadence or Synopsys tools. + Experience in writing timing constraints - Save Job - Email - More

View Job Details : Hardware Design Engineer (ASIC)
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Design For Test (DFT) Engineer

de.jobsyn.org - Intel - Allentown, PA

5 days ago - DFT tools such as Mentor Graphics Tessent, Synopsys DFT Compiler, DFTMax, TetraMax. **How - Save Job - Email - More

View Job Details : Design For Test (DFT) Engineer
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Senior Design Verification Engineer

de.jobsyn.org - NVIDIA - Santa Clara, CA

30+ days ago - checking tools such as Cadence (IEV), Jasper and Synopsys (Magellan / VC Formal) is a plus. + Experience - Save Job - Email - More

View Job Details : Senior Design Verification Engineer
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MoHE - Intel MDC Elite Internship

de.jobsyn.org - Intel - Kulim, Mys

11 hours ago - extraordinary. This provides the successful candidate with + Specialized Synopsys training with viva (5 weeks) + In-depth Intel training on pre & post - Save Job - Email - More

View Job Details : MoHE - Intel MDC Elite Internship
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FIP Physical Design and QA Engineer

de.jobsyn.org - Intel - Bengaluru, Ind

30+ days ago - experience. 2+ years of experience with physical synthesis and place and route using Synopsys Fusion Compiler or Cadence Genus/Innovus - Save Job - Email - More

View Job Details : FIP Physical Design and QA Engineer
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Electronic-Photonic Software Tools Engineer

de.jobsyn.org - Intel - Bengaluru, Ind

30+ days ago - industry standard EDA software such as Cadence, Mentor, Synopsys, etc. **Qualifications** **Minimum Qualifications - Save Job - Email - More

View Job Details : Electronic-Photonic Software Tools Engineer
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3DIC Flow Designer

de.jobsyn.org - Intel -

30+ days ago - flows using commercial tools from vendors such as Synopsys, Cadence, Siemens, Ansys, etc. + Focus on SI - Save Job - Email - More

View Job Details : 3DIC Flow Designer
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Sr. Product Engineer - Place & Route

de.jobsyn.org - Siemens Digital Industries Software - Seongnam, Kor

28 days ago - routing). + Hands-on experience with commercial place & route tools like Synopsys-ICC2/FC, Cadence-lnnovus or Aprisa - Save Job - Email - More

View Job Details : Sr. Product Engineer - Place & Route
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ASIC APR Technology Development Engineer

de.jobsyn.org - Intel - Phoenix, AZ

30+ days ago - Perl, Python or Ruby. - Cadence Innovus or Synopsys Fusion Compiler. - Semiconductor design rules - Save Job - Email - More

View Job Details : ASIC APR Technology Development Engineer
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Physical Design CAD Engineer

de.jobsyn.org - NVIDIA - Yokneam, Isr

30+ days ago - Familiarity with synthesis, place and route, STA EDA tools from Synopsys (DC/FC/PT), Cadence (Innovus/ - Save Job - Email - More

View Job Details : Physical Design CAD Engineer
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Senior Engineer

de.jobsyn.org - QuEST Global - Bangalore (Bengaluru), Ind

30+ days ago - Provides technical support/expertise for customers operating Synopsys test automation tools in a wide variety of application scenarios - Save Job - Email - More

View Job Details : Senior Engineer
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Physical Design Engineer (RTL2GDS)

de.jobsyn.org - Intel - Phoenix, AZ

19 days ago - ) flows using APR tools such as Synopsys ICC2 or Cadence INNOVUS tools. - At - Save Job - Email - More

View Job Details : Physical Design Engineer (RTL2GDS)
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SOC Verification Manager

de.jobsyn.org - Intel - San José, Cri

30+ days ago - permit. **Preferred Qualifications:** - Familiar with Synopsys tools **Inside this Business Group** - Save Job - Email - More

View Job Details : SOC Verification Manager
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Structural (Physical Design) Engineer Full Chip Lead

de.jobsyn.org - Intel - Bengaluru, Ind

30+ days ago - complex SoCs.Hands-on experience with industry standard Cadence or Synopsys tool suite, and other Sign-off tools from Siemens (Mentor - Save Job - Email - More

View Job Details : Structural (Physical Design) Engineer Full Chip Lead
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Product Yield Engineer

de.jobsyn.org - Intel -

7 days ago - e.g: V93K, T2K and J750 - Experience in Synopsys Yield Explorer or JMP will be an advantage - Analytical - Save Job - Email - More

View Job Details : Product Yield Engineer
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ASIC Physical Design Engineer, Proto

www.ziprecruiter.com - Block - San Jose, CA

13 days ago - years in combination with a MS degree * Expert in using Synopsys ICC2/Fusion Compiler and PrimeTime * Understanding - Save Job - Email - More

View Job Details : ASIC Physical Design Engineer, Proto
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ASIC Physical Design Engineer, Proto

www.ziprecruiter.com - Block - Chandler, AZ

13 days ago - years in combination with a MS degree * Expert in using Synopsys ICC2/Fusion Compiler and PrimeTime * Understanding - Save Job - Email - More

View Job Details : ASIC Physical Design Engineer, Proto
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ASIC Physical Design Engineer, Proto

www.ziprecruiter.com - Block - San Diego County, CA

13 days ago - years in combination with a MS degree * Expert in using Synopsys ICC2/Fusion Compiler and PrimeTime * Understanding - Save Job - Email - More

View Job Details : ASIC Physical Design Engineer, Proto
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